1. Field of the Invention
The present invention relates to a bus request control circuit which controls transmission of a request signal to request a right to use a bus.
2. Description of the Related Art
As a method of controlling access to a memory, proposed is a signal processing apparatus in Jpn. Pat. Appln. KOKAI Pub. No. 2000-92375. In the apparatus, when request signals are received from various signal processing circuits (called “master”) connected to a memory controller via buses, the memory controller selects a master having the highest-priority from the masters which outputted a request signal, and supplies image data written in the image memory to the selected master to allow the master to perform signal processing.
The above method is further explained. Each master usually has a buffer memory for temporarily storing data read from and/or to be written in the memory, and issues a request for access to the memory, according to the free space of the buffer memory. Specifically, if the buffer memory has a free space, the master issues the request signal and stores data read from the memory in a buffer memory. A bus request control circuit provided in each of the masters performs control of output of such a request signal.
The bus request control circuit (SDRAM bus interface) has a structure as shown in FIG. 5, for example. The bus request control circuit illustrated in FIG. 5 comprises a NOR circuit 101 and a flip-flop circuit 102. In the bus request control circuit of FIG. 5, the NOR circuit 101 is connected with an input section for a signal indicating available space of the buffer memory (hereinafter referred to as “buffer state signal”) and an output section of the flip-flop circuit 102. An output section of the NOR circuit 101 is connected to a set (set) terminal of the flip-flop circuit 102. An input section for a request acknowledge signal from a memory controller (not shown) is connected to a reset (rst) terminal of the flip-flop circuit 102.
The bus request control circuit having the above structure operates as follows. For example, supposing that a buffer state signal when the buffer memory is full is “1”, the NOR circuit 101 outputs “1” only if both the buffer state signal and the output of the flip-flop circuit 102 are “0”. When the NOR circuit 101 outputs “1”, the flip-flop circuit 102 outputs “1”, and transmission of a request signal is permitted. When a request acknowledge signal is input to the flip-flop circuit 102, the output of the flip-flop circuit 102 is reset to “0”. Thereby, the master checks again whether the buffer memory has an available space, and issues a request signal if the buffer memory still has an available space. This operation is illustrated in the timing chart of FIG. 6. Specifically, a bus request control circuit having a structure as shown in FIG. 5 continuously transmits a request signal as long as the buffer memory has an available space.